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       DC是把HDL描述的電路綜合為跟工藝相關(guān)的、門級電路。并且根據(jù)用戶的設(shè)計要求，在時序和面積，時序和功耗上取得佳的效果。在floor planning和placement和插入時鐘樹后 返回DC進(jìn)行時序驗證。其高版本被稱為DC Ultra。在Synopsys軟件中完整的綜合方案的核心是DC UltraTM，對所有設(shè)計而言它也是好級別的綜合平臺。DC Ultra添加了全面的 數(shù)據(jù)通路和時序優(yōu)化技術(shù)，并通過工業(yè)界的反復(fù)證明。

 第一階段

       綜合的定義；ASIC design flow；Synopsys Design Compiler的介紹；Tcl/Tk 功能介紹；Synopsys technology library；Logic synthesis的過程；Synthesis 和layout的接口——LTL；Post_layout optimization；SDF文件的生成；其他高級綜合技巧與總結(jié)。
　　Overview?
　　
　　 This course covers the ASIC synthesis flow using Design Compiler -- from reading in an RTL design (Verilog and VHDL) to generating a final gate-level netlist. You will learn how to read in your design file(s), specify your libraries, constrain a complex design for area and timing, partition your design? hierarchy for synthesis, apply synthesis techniques to achieve area and timing closure, analyze the synthesis results, and generate output data that works with downstream layout tools. You will verify the logic equivalence of synthesis transformations (such as Datapath optimizations and Register Retiming) to that of an RTL design using Formality. The course includes labs to reinforce and practice key topics discussed in lecture. All the covered commands and flows are printed separately in a 4-page Job Aid which the student can refer to back at work.
　　
　　 Objectives?
　　
　　 At the end of this workshop the student should be able to:?
　　 ◆Create a setup file to specify the libraries that will be used?
　　 ◆Read in a hierarchical design?
　　 ◆Partition a design's hierarchy optimally for synthesis?
　　 ◆Constrain a complex design for area and timing, taking into account different environmental attributes such as output loading, input drive strength, process, voltage and temperature variations, as well as post-layout effects such as clock skew and net parasitics?
　　 ◆Select the appropriate compile flow for your project?
　　 ◆Execute the recommended synthesis techniques within each compile flow to achieve area and timing closure?
　　 ◆Perform test-ready synthesis when appropriate?
　　 ◆Verify the logic equivalence of a synthesized netlist to that of an RTL design?
　　 ◆Write DC-Tcl scripts to constrain and compile designs?
　　 ◆Generate and interpret timing, constraints and other debugging reports?
　　 ◆Understand the effect that RTL coding style can have on synthesis results?
　　 ◆Generate output data (netlist, timing/area constraints, physical constraints scan-def) that works with downstream physical design?or?layout tools?
　　
　　 Audience Profile
　　
　　 ASIC digital designers who are going to use Design Compiler to synthesize Verilog?or?VHDL RTL modules to generate gate-level netlists.
　　
　　 Prerequisites
　　
　　 To benefit the most from the material presented in this workshop, you should:
　　 ◆Understand the functionality of digital sequential and combinational logic?
　　 ◆Have familiarity with UNIX and a UNIX text editor of your choice?
　　 ◆No prior Design Compiler knowledge?or?experience is needed?
　　
　　第二階段
　　
　　 Unit 1
　　 ◆Introduction to Synthesis
　　 ◆Setting Up and Saving Designs
　　 ◆Design and Library Objects
　　 ◆Area and Timing Constraints
　　 ◆Setting Up and Saving Designs

• Loading Technology and Design Data
• Design and Library Objects
• Timing Constraints

　　 Unit 2
　　 ◆Partitioning for Synthesis
　　 ◆Environmental Attributes
　　 ◆Compile Commands
　　 ◆Timing Analysis
　　 ◆More Constraint Considerations
　　

• Compiling RTL to Gates
• Timing Analysis

Unit 3
◆More Constraint Considerations
◆Multi-Clock Designs
◆Synthesis techniques and Flows
◆Post-Synthesis Output Data
◆Conclusion
Congestion Analysis and Optimization

Unit 4

Unit 5

Clock Tree Synthesis

Multi Scenario Optimization

?

Unit 6

Design Planning

Routing and Crosstalk

Chip Finishing and DFM

Customer Suppor

第三階段

第一部分
unit 1. Introduction to Synthesis
? Execute the basic steps of synthesis on a simple design
? Use two commands to modify the partitioning of a design
? Gain familiarity with SolvNet ,your essential resource for?
　　solving your design compiler problems
unit 2. Setup, Libraries and Objects
unit 3. Partitioning for Synthesis
unit 4. DC Tcl - An Introduction

第二部分
unit 5. Timing and Area
?Constrain simple designs for area, timing and design
　　rule constraints (DRC)
? Generate ,view and analyze timing and DRC reports
unit 6. Environmental Attributes
unit 7. Design Rules and Min Timing
unit 8.Timing Analysis

第三部分
unit 9.Multiple Clock/Cycle Designs
? Constrain and analyze multi-clock,
　　asynchronous and multi-cycle path designs
? State several key steps that occur during a default compile?
? Enable Design Compiler to work harder in fixing design violations
? Describe some issues that surround synthesis and where to find additional information?

unit 10. Optimization

unit 11.Compile Strategies

unit 12. Before,During and After　

        從事ASIC 設(shè)計與驗證的工程師，希望更深入了解Design Compiler和芯片綜合（chip synthesis）技術(shù)的工程師，希望從事ASIC設(shè)計工程師的理工科背景大四學(xué)生或碩士研究生。

        學(xué)員學(xué)習(xí)本課程應(yīng)具備下列基礎(chǔ)知識：
        ◆ 對數(shù)字集成電路設(shè)計有一定理解；
        ◆ 了解Verilog/VHDL 語言。