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培訓(xùn)方式以講課和實(shí)驗(yàn)穿插進(jìn)行。

Cadence? Incisive? Enterprise Simulato主要利用系統(tǒng)級(jí)至門(mén)級(jí)的涵蓋率來(lái)驅(qū)動(dòng)功能驗(yàn)證和除錯(cuò)分析進(jìn)一步促進(jìn)的驗(yàn)證的效率及可預(yù)測(cè)性。Cadence Incisive Enterprise Simulator?提供testbench制作、共用和分析能力，可從系統(tǒng)級(jí)至RTL再到門(mén)級(jí)驗(yàn)證其設(shè)計(jì)，利用此環(huán)境從計(jì)劃至完成皆可支援涵蓋范圍驅(qū)動(dòng)的運(yùn)算法，而其原位編譯的模組可在傳統(tǒng)同步模擬加速並同時(shí)模擬關(guān)于behavior、transation(TLM)?、RTL和門(mén)級(jí)模型，以達(dá)到有效改善同步模擬的不良性能。它也支援工業(yè)標(biāo)準(zhǔn)的驗(yàn)證語(yǔ)言並且與開(kāi)放驗(yàn)證運(yùn)算法相容(OVM)，因此工程師能迅速簡(jiǎn)單地整合Cadence Incisive Enterprise Simulator以建立所需要的驗(yàn)證流程。

COURSE OUTLINE

MDV (Metric Driven Verification) foundations workshop

·?????????MDV Foundations introduction

–??MDV Foundations Planning

–??Introduction to Planning

·?????????Verification Plan Development

–??Lab 1: Launching Your First Regression

–??Lab 2: Review the Default vPlan View in Enterprise Manager

–??Lab 3: Creating Reusable Verification Plans

–??Lab 4: Creating a Top Level Verification Plan

–??Lab 5: Detecting Changes in the New Specification

–??Lab 6: Review the vPlan in vManager

·?????????MDV Foundations Infrastructure ?

–??Lab 1: Your First Enterprise Manager Regression

–??Lab 2: Integrating project build and run

·?????????MDV Foundations Management

–??Lab 1: Create your own first failures view

–??Lab 2: Rerun Failures

–??Lab 3: vPlan Analysis

–??Lab 4 : Report generation

?

Low Power Verification Workshop

???????????Introduction

–????????Introduction to Low Power Terminology

–????????CPF Creation

–????????Lab: Understanding the power information from a CPF file - Solution

???????????Low Power Simulation Verification

–????????Verification Planning and Metrics for Low Power

–????????Low-Power Simulation

–????????TCL Commands for Debug

–????????Debugging with SimVision

–????????Automatic Assertions

–????????Lab: Low-Power Simulation Debug

Assura Verification

The Assura? Verification course covers aspects of using the Assura DRC and Assura LVS tools for design rule checks, short location, and layout-versus-schematic checks. In labs, the student executes DRC and LVS and debugs error results.

Learning Objectives
In this course you will:
? o Verify your physical IC design with Assura Verification?
? o Set up and run DRC and LVS?
? o?Locate and display results from DRC and LVS runs?
? o Run verification in various input and run modes

Audience
? o CAD Developers
? o Design Engineers
? o? Layout Designers

Prerequisites
? o Layout design experience
? o Physical verification experience
? o UNIX OS

Course Agenda

Unit 1

? o?Introduction?
? o?Using Assura Verification?
? o?Operational details?
? o?Inputs and outputs?
? o?Interactive debugging environment?
? o?DRC and LVS runs
? o?Running design-rule checks (DRC)?
? o?DRC error debugging techniques?
? o?Error Layer Window?
? o?Setting up DRC run parameters

Unit 2

? o?Running design rule checks (continued)?
? o?Antenna check?
? o?Density check
? o?Running layout versus schematic (LVS) checks?
? o?Understanding and debugging LVS check reports?
? o?Setting up LVS run parameters?
? o?Displaying errors using the graphical user interface?
? o Locating LVS errors

Unit 3

? o Running layout versus schematic checks (continued)?
? o?Debugging LVS with multiple errors?
? o?Using the main debugging tools?
? o?Mismatched nets and mismatched devices?
? o?Shorts locator and opens locator?
? o?Malformed devices?
? o?Pins, parameters, and rewire tools
? o?Unguided debugger lab module?
? o?Running an electrical rules check (ERC)