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• Verifying a design
• Debugging a failed design

• Optimize Formality for common hardware design transformations
• Increase debugging capability through techniques such as pattern analysis
• Maximize verification performance

• Describe where Formality fits in the design flow
• Read a reference design and the libraries for that design into Formality
• Read a revised design and the libraries for that design into Formality
• Set up for verification interactively and with scripts
• Handle common design transformations for easiest verification
• Guide Formality in matching names between two designs
• Verify that two designs are equivalent
• Debug designs proven not to be equivalent
• Optimize reads, compare point matching and verification

• Introduction
• Controlling Formality
• Setting up and running Formality
• Debugging designs proved not equivalent

• Design transformations and their effect on equivalence checking
• Advanced debugging
• Maximizing performance

• Preparing for STA on your design, including investigating and analyzing the clocks that dictate STA results
• Validating inherited PrimeTime run scripts
• Leveraging the latest PrimeTime best practices to create new run scripts
• Identifying opportunities to improve run time
• Performing static timing analysis
• Providing ECO fixing guidance to downstream tools

• Interpret the essential details in a timing report for setup and hold, recovery and removal, and clock-gating setup and hold
• Generate timing reports for specific paths and with specific details
• Generate summary reports of the design violations organized by clock, slack, or by timing check
• Validate, confirm, debug, enhance, and execute a PrimeTime run script
• Create a PrimeTime run script based on seed scripts from the RMgen utility
• Identify opportunities to improve run time
• Create a saved session and subsequently restore the saved session
• Identify the clocks, where they are defined, and which ones interact on an unfamiliar design
• Reduce pessimism using path-based analysis
• Use both a broad automatic flow for fixing setup and hold violations and a manual flow for tackling individual problem paths.

• A basic understanding of digital IC design
• Familiarity with UNIX workstations running X-windows
• Familiarity with vi, emacs, or other UNIX text editors

• Does your design meet timing?
• Objects, Attributes, Collections
• Constraints in a timing report
• Timing arcs in a timing report
• Control which paths are reported

• Summary Reports
• Create a setup file and run script
• Getting to know your clocks
• Analysis types and back annotation

• Additional checks and constraints
• Path-Based Analysis and ECO Flow
• Emerging Technologies and Conclusion

• Pinpoint the cause and determine the effects of check_timing and report_analysis_coverage warnings
• Execute seven PrimeTime commands and two custom procedures to trace from the warning to the cause and explore objects in that path
• Systematically debug scripts to eliminate obvious problems using PrimeTime
• Independently and fully utilize check_timing and report_analysis_coverage to flag remaining constraint problems
• Identify key pieces of a timing report for debugging final constraint problems

• Have taken PrimeTime 1

• Script writing using Tcl
• Reading and linking a design
• Writing block constraints
• Generating and interpreting timing reports using report_timing and report_constraint commands

• Lab 1 A Guided Tour of the Tools of the Trade
• Lab 2 Choose the Correct Command and Apply It

• Lab 3 Find and Debug Potential Constraint Problems

• Generate test patterns for stuck-at faults given a scan gate-level design created by DFT Compiler or other tools
• Describe the test protocol and test pattern timing using STIL
• Debug DRC and stuck-at fault coverage problems using the Graphical Schematic Viewer
• Troubleshoot fault coverage problems
• Save and validate test patterns
• Troubleshoot simulation failures
• Diagnose failures on the ATE

• What is manufacturing test?
• Why perform manufacturing test?
• What is a stuck-at fault?
• What is a scan chain?

• Incorporate TetraMAX?ATPG in a design and test methodology that produces desired fault coverage, ATPG vector count and ATPG run-time for a full-scan or almost full-scan design
• Create a STIL Test Protocol File for a design by using Quick STIL menus or commands, DFT Compiler, or from scratch
• Use the Graphical Schematic Viewer to analyze and debug warning messages from Design Rule Check or fault coverage problems after ATPG
• Describe when and how to use at least three options to increase test coverage and/or decrease the number of required test patterns
• Save test patterns in a proper format for simulation and transfer to an ATE
• Validate test patterns using Verilog Direct Pattern Validation or MAX Testbench
• Use TetraMAX diagnosis features to analyze failures on the ATE

• Understanding of the differences between manufacturing and design verification testing
• Stuck-at fault model
• Internal and boundary scan chains
• Scan shift and capture violations
• Major scan design-for-test rules concerning flip-flops, latches, and bi-directional/tri-state drivers
• Understanding of digital IC logic design
• Working knowledge of Verilog or VHDL language
• Familiarity with UNIX workstations running X-windows
• Familiarity with vi, emacs, or other UNIX text editors

• Introduction to ATPG Test
• Building ATPG Models
• Running DRC
• Controlling ATPG

• Minimizing ATPG Patterns
• Writing ATPG Patterns
• Pattern Validation
• Diagnosis
• Conclusion

• Describe the need for At-Speed testing
• List the At-Speed fault models available
• Describe the two launch techniques for at-speed faults
• Successfully edit a stuck-at SPF file to suit at-speed fault model
• Define the timing exceptions
• Automate the process of script generation for TetraMAX, using PrimeTime. This script will take care of the false and multi-cycle paths
• Modify a given stuck-at fault model script to run for an at-speed fault model
• State the steps required to merge transition and stuck-at fault patterns to reduce the overall patterns
• Automatically create scripts that can be used in PrimeTime to perform test mode STA
• Describe the SDD flow
• Describe the flow needed to successfully use the PLL present in your design to give the at-speed clock during capture mode
• State the steps needed to perform path-delay ATPG
• Understand the fault classification in path-delay ATPG

• Scan Architecture and ATPG
• Stuck-At fault model ATPG with TetraMAX
• SPF file

• Introduction of At-Speed defects
• Source of Test Escapes and chip failure
• Requirements for At-Speed testing
• Popular fault models for At-Speed testing

• Transition Fault model
• Path Delay Fault model
• At-Speed Fault Detection Method
• Techniques to Launch and Capture a Fault

• STIL file
• Modifications to STIL file for At-Speed testing
• Generic Capture Procedures

• Timing Exceptions
• Automated Way to Generate Timing Exceptions form PrimeTime

• TetraMAX Scripts for Transition ATPG
• Design Guidelines
• Flow Considerations and Requirements
• Pattern Merging
• Automated way to generate the scripts for PrimeTime to perform testmode STA

• What is a Small Delay Defect ATPG
• How to use PrimeTime to Generate the Slack Data
• ATPG Flow in TetraMAX

• Requirement of PLL for At-speed faults
• The various clocks in PLL flow
• Use QuickSTIL to generate the SPF

• TetraMAX scripts for Path Delay ATPG
• Fault Classification for Path Delay Faults
• Generating Paths for TetraMAX Using PrimeTime
• Reconvergence Paths
• Hazard Simulation

• Conclusion
• Topics Covered
• Fault model and Features of TetraMAX
• Solvnet Resources